1. Field of the Invention
The present invention relates to an ESD protection circuit and particularly to an ESD protection circuit with high substrate-triggering efficiency.
2. Description of the Related Art
Electrostatic discharge (ESD) is a transient process of high energy transformation from external to an integrated circuit (IC) internal when the IC is floated. The total discharge process lasts about 100 ns, and several hundred volts, up to several thousand volts are transferred during an ESD event. Such high voltage transformation causes the gate oxide of the input stage to breakdown and further cause circuit malfunctions. As gate oxide thickness is continuously scaled down, it becomes important to design a protection circuit or device to protect the gate oxide that effectively discharges ESD stress.
The models related to ESD stress include the human body model (HBM), machine model (MM) and charged device model (CDM). For commercial IC products, the general ESD specification requires that IC products must pass certain ESD tests, for example, HBM ESD stress of greater than +/−2 kV, MM ESD stress of greater than +/−200V and CDM ESD stress of greater than +/−1 kV, respectively. In order to sustain such high ESD voltage, efficient and robust protection circuits, which usually require large layout dimensions, should be used.
To achieve the above object, several protection circuits, including the following, have been proposed.